Today, we are going to take a look at 5G focused accelerator. Given the rise in the interest of Enterprise private 5G networks, there are demands for general purpose platforms that can run 5G network stack as well as providing additional microservices on or near the systems running the 5G networks. To maximize performance on these platforms, generally x86, we need another type of accelerator specifically for the 5G workload.

Many accelerators are based upon a FPGA to reduce development cost and faster time to market. Intel has promoted their N3000 FPGA ( https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/intel-fpga-pac-n3000/overview.html ) Smart NIC platform for accelerating 5G workloads. FPGA based Smart NICs has the flexibility of integrating additional IPs to provide acceleration of application specific workloads. FPGA giant Xilinx, has a competing solution called T1 ( https://www.xilinx.com/applications/wired-wireless/telco.html ) that also features onboard 25Gbps LAN ports to reduce number of devices that needs to be plugged into the system.

These cards differ from other Smart NICs in that these are designed to offload/accelerate Forward Error Correction (FEC) that is essential in 5G communications. Usage of FEC can control errors in packet delivery over unreliable wireless channels by encoding the message with certain redundancy so complete packets can be reconstructed even if there are information missing or have errors. These errors can be detected through the addition of LDPC (Low Density Parity Check) codes. Due to the low latencies required, significant compute power is required to maintain acceptable performance. Accelerators solve these problems with specialized function blocks that can efficiently generate FEC and LDPC codes with much lower energy use as compared to using a general-purpose CPU. Usage of these accelerators are making enterprise focused small cell 5G network possible. In typical enterprise scenarios, active connection count is significantly smaller than the typical use case of telecom operators. A single FEC accelerator is capable of servicing a single RU which then can support the typical user count in this use case.

There are competing technology trying to serve the same product niche. Intel is promoting their eASIC as an alternative to their FPGA. eASIC stands as an intermediary technology between FPGA and ASIC. The main advantage is portability of FPGA IP into eASIC designs without the long development time of ASIC. Being an intermediary solution, it sits in the happy middle regarding die size, power, and price. However, it does miss out on the FPGA’s ability to update the internal IP to provide new or upgrade functionalities.

There are a lot of technologies that needs to come together to bring 5G on general purpose x86 platform to fruition. We’re at the cusp of breaking through and making mass deployment of these private 5G infrastructure a reality. It is exciting time for telecommunications sector, and we hope you’ll join us for the ride.